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Françoise in 3D
Jan. 28, 2010
I just finished putting together a presentation for the upcoming BiTS Workshop March 7-10, 2010 taking place in my backyard in Mesa, AZ. Read More>>
From the Board Room
Jan. 04, 2010
Well, 2010 is here and we want to wish all our readers a happy and prosperous New Year! Read More>>
From Different Dimensions
Jan. 28, 2010
The following commentary piece by Electronic Design Europe's editor-in-chief, Paul Whytock, gives designers some insight on some recent developments in 3D research collaboration between Soitec and Leti, and what that means for designers. Read More>>
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Forums (6 forums , 9 discussions)

Forum Structure
 

Design Forum (Discussions: 2)
Technlogy Q&A (Discussions: 1)
Last Post: Re:Design Issues
By Françoise Von Trapp on Jan. 19, 2010
Last Post: High Aspect Ratio TSVs: why we... (concluded)
By Françoise Von Trapp on Feb. 03, 2010
EV Group Forum Series (Discussions: 1)
Last Post: Re:The Advances of Lithography... (concluded)
By Françoise Von Trapp on Oct. 17, 2009
Last Post: Re:Strategic Importance and Ch... (concluded)
By Françoise Von Trapp on Oct. 04, 2009
Test Forum (Discussions: 1)
Last Post: Re:On the road to resolving te... (concluded)
By Françoise Von Trapp on Dec. 21, 2009
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3D In-Depth (17 postings)

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By Françoise Von Trapp On Jan. 14, 2010
At MIT Lincoln Labs (MITLL), R&D processes developing 3D chips using silicon-on-insulator (SOI) wafers is the sole focus. As Phil Garrou, Ph.D. Read More>>
By Françoise Von Trapp On Jan. 11, 2010
Reporting progress for CEA-Léti was 3D program manager Mark Scannell, who notes an overall shift in what’s driving Léti's 3D developments. Read More>>
By Françoise Von Trapp On Jan. 11, 2010
At last month’s 3D Architectures for Semiconductor Integration and Packaging Conference, coordinated by RTI International, three government-funded research institutes – RTI, CEA-Leti, and MIT Lincoln Laboratories reported on the status of their progress in the 3D integration space. Read More>>
By Françoise Von Trapp On Dec. 16, 2009
I think maybe the design community is tired of being referred to as “a limitation” just because the tools aren’t ready yet. I think they are also tired of being the scape goat. Read More>>
By Françoise Von Trapp On Dec. 07, 2009
Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are vital to a multitude of semiconductor applications such as MEMS, compound semicond Read More>>
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Sponsored Site Tour (7 postings)

Most Recent
 
By Françoise Von Trapp On Dec. 01, 2009
If your company is located in France, and/or is involved in micro and nanotechnologies for microelectronics, chances are it’s either a spin out of Leti, its parent organization CEA, or is closely tied in ongoing collaboration to this major European research center for applied electronics. At least that is the impression I came away with after visiting Leti at its Minatec campus in Grenoble, France, as well as four other companies (Alchimer, Soitec, Replisaurus/S.E.T. Read More>>
By Françoise Von Trapp On Nov. 09, 2009
It’s not often that a company gets a do-over. Tegal France is one of the lucky ones. In fact, when Nicolas Launay, R&D director and general manager, referred to the company as a start-up, I did a double-take. Didn’t a company have to be VC-funded, and brand-new to be considered a start-up? Read More>>
By Françoise Von Trapp On Nov. 09, 2009
It’s only fitting that Replisaurus’s equipment division, SET Smart Equipment Technology, which is located in Saint Jeoire, France, found its way into the Tour de France in 3D. After all, the town is on the route of the real Tour de France. Read More>>
By Françoise Von Trapp On Nov. 03, 2009
In an understated research lab and recently upgraded demo facility located just outside Paris in Massy, France, Alchimer scientists are working diligently to prove the readiness of an elegant and innovative electrochemical-based process for the growth of nanometric thin films of various types on both conducting and semiconducting surfaces. The technology has the potential to revolutionize process integration and cost models for 3D TSVs. Read More>>
By Françoise Von Trapp On Nov. 02, 2009
A walk across the impressive Bernin, France campus that is home to two of Soitec Group’s three divisions takes you past three production-level fab facilities – aptly named Bernin 1, Bernin 2, and Bernin 3, plus a development facility. The company’s three-stage business model encompasses innovation, licensing, and production to allow for seamless transfer of full technology and process control to customers as a turnkey solution. Read More>>
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Videos (10)

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White Papers (9 files)

3D IC Integration White paper FINAL.pdf 3D Integration: A Progress Report 11/16/2009 11:55am
LDC-IEEE3D.pdf Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling. 11/05/2009 1:32pm
EMPC 2009 Modelisation of TSV-CMOS coupling.pdf Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology 08/04/2009 10:49am
ECTC 2008 TSV for CMOS image Sensors.pdf TSV Technology for CMOS Image Sensor Packaging 08/04/2009 10:55am
ECTC 2009 TSV pre-process.pdf Via First Approach Optimization for TSV Applications 08/04/2009 11:11am
ECTC 2009 DRy Film lithography.pdf Cost-Effective Dry Lithography for TSV Technology 08/04/2009 11:13am
IITC Focus on 3D WLP.pdf 3D WLP Schemes Address Industrial Needs 08/04/2009 11:17am
ECTC2009 Temporary bonding.pdf Integration of a Temporary Carrier in a TSV Process Flow 08/04/2009 10:40am
http://www.suss.com/contact?adr=41&snc=20641 Thin Wafer Processing for 3D TSV Applications Workshop 08/04/2009 11:25am
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Message Board (1)

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#3 Submitted by Françoise Von Trapp on September 25, 2009 - 2:01pm.
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Press Releases (52 postings)

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By Françoise Von Trapp On Feb. 04, 2010
In a deal that is expected to generate economical new process options for the 3D integration market, Alchimer S.A., a provider of nanometric deposition technology for semiconductor interconnects and through-silicon vias (TSVs), and KPM Tech Co. Read More>>
By Françoise Von Trapp On Jan. 28, 2010
In a double-barreled press release, SUSS MicroTec announced the sale of its Test Systems Division to Cascade Microtech, Inc., a worldwide supplier of precise electrical measurement and test of integrated circuits; as well as a strategic partnership between the two companies to address the growing device complexities of emerging semiconductor technologies such as 3D TSV manufacturing and test. Read More>>
By Françoise Von Trapp On Jan. 21, 2010
Global research center, Leti, located in Grenoble France, and 3D IC EDA company R3Logic,announced that they will combine their expertise in 3D silicon integration and packaging. Read More>>
By Françoise Von Trapp On Jan. 12, 2010
Rudolph Technologies, Inc. announced it has received multiple orders for its NSX® and WaferScanner™ Inspection Systems from STATS ChipPAC Ltd. The systems will be used for high-throughput inspection during each step of the eWLB (embedded wafer-level ball grid array) process. Shipments commenced in 4Q09 and will continue through 1Q10. Read More>>
By Q3D Notes On Jan. 07, 2010
A new industry emphasis on 3D memory technology has prompted the 2010 IEEE International Interconnect Technology Conference (IITC) to expand the conference's technical program with a session on alternative back-end memory technologies. Read More>>
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Feb 04, 10
TSV – Is it a Wire or a Device? Online Discussion Feb. 8-12, 2010
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Dec 01, 09
Tour de France in 3D: A Retrospective
 
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